Analog phase locked loops (PLLs) do not scale well across process technologies. The term “scale” herein refers to converting or translating a circuit design manufactured and optimized to operate in a process manufacturing technology to another advanced process manufacturing technology with smaller dimensions and different transistor behavior. For example, a PLL design scaled from a 45 nm Complementary metal-oxide-semiconductor (CMOS) process manufacturing technology to a 32 nm CMOS process manufacturing technology requires a complete re-design of operation points for the analog circuits of the PLL. Such scaling of circuit design adds to the overall cost of the design because more time is spent re-designing the circuit when the circuit is ported or scaled from one process technology to a more advanced process technology.